The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for integrating an inductor in a semiconductor die. The inductor can be formed on the surface of a semiconductor device substrate in a spiral shape created in a plane that is parallel to the substrate surface.
As semiconductor technologies evolve, the inductor embedded in a semiconductor device can be formed of copper by using an ultra-thick metal (UTM) process. Copper inductors have emerged as an effective alternative to further reduce power losses of a semiconductor chip. In a copper inductor, the copper structure of the inductor can be formed by using damascene processes. In this technology, a dielectric layer is patterned to form a trench. After the patterning, a barrier layer may be deposited on the trench. A seed layer may be deposited on the barrier layer to provide better adhesion of copper. Furthermore, through an electrochemical plating process, metal materials such as copper fill the trench to form metal structures such as metal lines and vias.
Damascene processes can be divided into categories, namely single damascene processes and dual damascene processes. In single damascene technology, a metal via and its adjacent metal line may have different process steps. As a result, each may require a chemical mechanical planarization process to clean the surface. In contrast, in dual damascene technology, a metal via and its adjacent metal line may be formed within a single trench. As a result, two dielectric patterning processes and one CMP process are required in a dual damascene process to form the metal via and its adjacent metal line.
In a copper inductor, the copper structure of the inductor may be enclosed by a dielectric layer. There may be a concentration of stress in the areas adjacent to the interface between a corner of the copper structure and its adjacent dielectric layer. As a result, dielectric cracks may occur in the area adjacent to the copper structure. Such dielectric cracks may lead to an unreliable semiconductor device.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.